CV

This is my CV

Contact Information

Name Aditya B Pattavardhanam
Professional Title Student
Email aditya.pattavardhanam@gmail.com

Professional Summary

Electronics and Communication Engineering student at UVCE focused on VLSI, mixed-signal circuits, and avionics power systems. Research Intern at IISc Aerospace Engineering and Incoming Summer Fellow at IIT Madras.

Experience

  • 2025 - present

    Bengaluru, India

    Research Intern – Avionics & Propulsion | Team Lead (Avionics)
    IISc, Dept. of Aerospace Engineering (Project Urdhyuth)
    Guided by Prof. Dineshkumar Harursampath (IISc) and Prof. Ramesh Gupta (NITTR-Bhopal), working on propulsion battery systems and BMS development.
    • Developing a Power Management System in MATLAB involving load modeling, protection logic, and subsystem interface for an eVTOL platform
    • Co-designed Li-Ion NMC battery architecture and implemented BMS functions for monitoring, balancing, and safety protection
    • Actively researching Hardware-Based BMS architectures
  • 2026 - 2026

    Chennai, India

    Incoming Summer Research Fellow
    IIT Madras, Dept. of Electrical Engineering
    • Selected for the Summer Fellowship Programme 2026 based on academic credentials
    • To work on Integrated Circuit Design
  • 2023 - present

    Bengaluru, India

    Coordinator Design & Prototyping | Co-Lead Product Development
    MARVEL UVCE, R&D Lab
    • Mentored student electronics designs involving PCB, FPGA, and signal processing
    • Co-leading product development cohort focusing on end-to-end hardware solutions
    • Co-developed AIR-001 syllabus emphasizing avionics-oriented electronics design
    • Authored “Before We Scale — Design at the Edge of Intent” for the product cohort
  • 2024 - present

    Bengaluru, India

    Podcast Editor and Host
    UVCE Graduates Association
    Edited and hosted 13 episodes across Seasons 4–6 of UVCE Chronicles.
  • 2024 - 2024

    Bengaluru, India

    Representative Committee, Coordinator – Power Electronics Society (PELS)
    IEEE UVCE

Education

  • 2023 - 2027

    Bengaluru, India

    Bachelor of Technology
    University of Visvesvaraya College of Engineering (UVCE)
    Electronics & Communication Engineering
    • CGPA: 9.07/10 (5th Semester)
  • - 2023

    Bengaluru, India

    BASE PU College, Rajajinagar
    XII — Karnataka State Board
    • Score: 91%
  • - 2021

    Bengaluru, India

    Daffodils English School
    X — ICSE
    • Score: 91%

Projects

  • CMOS Current Mirror Design & Verification

    Full analog design flow on SKY130A — schematic to post-layout verification on Linux.

    • Transient, corner, and Monte Carlo simulations; full DRC, LVS, parasitic extraction
    • Automated GDS, DRC, and LVS checks using GitHub Actions
  • HeartGuard — ECG Anomaly Detection Device

    Real-time arrhythmia detection device with custom analog front-end and wireless streaming.

    • Analog front-end using TI ADS1298 (8-channel, 24-bit ECG AFE) with custom signal conditioning
    • Custom 4-layer PCB in Altium integrating ADS1298, STM32F411 (Cortex-M4), and BLE module
  • Hardware-Aware Spectrum Monitoring with Jammer-like Anomaly Detection

    Passive spectrum sensing platform for real-time channel occupancy and interference analysis.

    • StrongARM latch comparator achieving 6–7 mV sensitivity and 10 ns decision time
    • Validated across noise-only, signal-present, and jammer conditions using LoRa and FPGA
  • Hardware Trojan Detection

    RTL-level trojan injection and side-channel detection pipeline.

    • Designed and injected RTL-level hardware trojans in Verilog to model microarchitectural vulnerabilities
    • 70,000 cycles of constrained-random stimulus; Python-based switching activity detection pipeline
  • CanSat — Can-Sized Satellite

    Leading power subsystem design for a can-sized satellite platform.

    • Defined power architecture and voltage domains
    • Executed power budgeting from component datasheets and duty cycles to size regulators

Skills

Digital Design: RTL (Verilog, SystemVerilog), FPGA (Vivado, Quartus), Verification Testbenches
Analog / CMOS: CMOS Circuit Design, SPICE-level Analysis, Signal Conditioning
EDA Tools: Vivado, Altium Designer, KiCad, LTspice, Ngspice, MATLAB
Programming: Verilog, SystemVerilog, SPICE, C/C++, Python, Java
Domains: VLSI, Battery Management Systems, Power Management, Avionics

Awards

  • 2025
    1st Place – MARVEL CTARA Hackathon 2025
    MARVEL UVCE
  • 2025
    1st Place – Impetus 2025 AvionX Electrical Subsystem
    IEEE UVCE
  • 2024
    Winner – SiliconSprint Digital Design Hackathon
    IEEE NITK & RVCE
  • 2023
    1st Place – Kagada 2023 Project Track
    IEEE UVCE
  • 2023
    1st Place – Science Spectrum
    Christ University
  • 2024
    Best Performer Award D-P-001 Level 1
    MARVEL UVCE

Certificates

  • VLSI Chip Design and Simulation with Electric VLSI EDA Tool - L&T EduTech / Coursera
  • Fundamentals of Digital Design for VLSI Chip Design - L&T EduTech / Coursera
  • FPGA Design for Embedded Systems - University of Colorado Boulder / Coursera
  • Altium Designer - Altium Education
  • ROS 2 Fundamentals - Udemy

Interests

Music: Performing guitarist and vocalist
Sports: Table tennis enthusiast